1. Field of the Invention
The present invention relates to a pattern data creating method, a computer program product, and a semiconductor device manufacturing method.
2. Description of the Related Art
In recent years, there has been a striking progress in the semiconductor manufacturing technology and semiconductor device of the 50 nm half-pitch generation are being mass-produced. The miniaturization of semiconductor device symbolized by the 50 nm half-pitch generation is achieved by significant advance in the micropattern forming technology such as the mask processing technology, the lithography processing technology, and the etching processing technology. In the times when pattern sizes formed on a wafer were sufficiently large, patterns having the same shape as the patterns drawn by the designer were formed as mask patterns on a mask. Then, the mask patterns were transferred over a resist applied on the wafer using an exposure apparatus. That enabled formation of patterns as designed on the wafer. However, with the miniaturization of the pattern sizes in recent years, the effect that the diffraction of the exposure light has on the dimensions on the wafer has been growing. Moreover, it is becoming difficult to perform mask manufacturing or wafer processing in order to form micropatterns with precision. For that reason, even if mask patterns having the same shape as the designed patterns are used, it is becoming increasingly difficult to form the pattern shapes as per the design on a wafer.
As a method of faithful formation of patterns having the same shape as the designed patterns on a wafer, the designed patterns on mask patterns are subjected to optical proximity correction (OPC) or process proximity correction (PPC).
As one of the PPC techniques, a method has been proposed in which variability in the processing conversion difference (between post-development resist shapes and post-etching pattern shapes) for each product can be reduced by arranging on the design layout dummy patterns that are irrelative to the circuit behavior. The dummy patterns are arranged on the design layout with a predetermined density so that a pattern coverage ratio (pattern forming ratio) inside the wafer plane is within a predetermined range.
Japanese Patent Application Laid-open No. 2006-60051 discloses a pattern designing method in which a dummy pattern forming region is split in a plurality of dummy pattern forming unit regions and a plurality of test ranges having a larger area than the dummy pattern forming unit regions are set in such a way that a part of each test range is overlapping. Then, tentative pattern coverage ratios are calculated for dummy patterns formed inside the dummy pattern forming unit regions within the test ranges and an averaging procedure is performed on the tentative pattern coverage ratios to calculate a final pattern coverage ratio. Subsequently, dummy patterns having the area equivalent to the final pattern coverage ratio are generated as patterns inside the dummy pattern forming unit regions.
However, by only adjusting the pattern coverage ratio as described in the abovementioned conventional technology, it was not possible to form patterns of accurate shapes on a wafer. This problem is attributed to the fact that, due to the difference in the occupancy of cells formed on a wafer, the attached amount of a side wall protective film or the etching time differs thereby resulting in variability in the processing conversion difference. To curb such variability in the processing conversion difference, it is necessary to newly obtain the PPC data for each product and then create a mask. That causes an increase in the development turnaround time (TAT).